A conventional single-ended sensing circuit in a memory senses a full-swing (VDD-to-VSS/Ground) signal that varies in access time due to cell current variations. Access time performance is limited by a weak bit within a cell array. Reading data “0” (logical 0) discharges a bit line with a full swing from VDD to ground and pulls down a global bit line for the read output. The bit line pre-charges back to VDD after the read operation is completed, which costs dynamic power consumption.